1. Field of the Invention
The present invention relates to a sign extension unit for extending a sign bit, i.e., the most significant bit of input data to the higher side of the input data.
2. Description of Related Art
FIG. 1 shows a sign extension circuit 301 according to a related art. The sign extension circuit 301 receives input data of byte length (8 bits), half-word length (16 bits), word length (32 bits), or double-word length (64 bits) and extends a sign bit thereof to form signed 64-bit output data. The circuit 301 has selectors MM8 to MM63 to receive input data consisting of bits IN0 to IN63 at the maximum. The selectors MM8 to MM15 select the bit IN7 or the bits IN(8+n) (n=0 to 7) and provide the selected bits as output bits OUT8 to OUT15. The selectors MM16 to MM31 select the bit IN7, the bit IN15, or the bits IN(16+n) (n=0 to 15) and provide the selected bits as output bits OUT16 to OUT31. The selectors MM32 to MM63 select the bit IN7, the bit IN15, the bit IN31, or the bits (32+n) (n=0 to 31) and provide the selected bits as output bits OUT32 to OUT63. The selection made by the selectors MM8 to MM63 is based on the length of input data.
Upon receiving input data of byte length consisting of bits IN0 to IN7, the selectors MM8 to MM63 select the bit IN7 serving as a sign bit of the input data for output bits OUT8 to OUT63, and the bits IN0 to IN7 are provided as they are as output bits OUT0 to OUT7. Namely, the sign bit of the input data is extended for the output bits OUT8 to OUT63, and the output bits OUT0 to OUT63 form sign-extended 64-bit output data. Upon receiving input data of half-word length consisting of bits IN0 to IN15, the selectors MM16 to MM63 select the bit IN15 serving as a sign bit of the input data for output bits OUT16 to OUT63, the bits IN0 to IN7 are provided as they are as output bits OUT0 to OUT7, and the selectors MM8 to MM15 select the bits IN8 to IN15 as output bits OUT8 to OUT15. Namely, the sign bit of the input data is extended for the output bits OUT16 to OUT63, and the output bits OUT0 to OUT63 form sign-extended 64-bit output data. Upon receiving input data of word length consisting of bits IN0 to IN31, the selectors MM32 to MM63 select the bit IN31 serving as a sign bit of the input data for output bits OUT32 to OUT63, the bits IN0 to IN7 are provided as they are as output bits OUT0 to OUT7, and the selectors MM8 to MM31 select the bits IN8 to IN31 as output bits OUT8 to OUT31. Namely, the sign bit of the input data is extended for the output bits OUT32 to OUT63, and the output bits OUT0 to OUT63 form sign-extended 64-bit output data. Upon receiving input data of double-word length consisting of bits IN0 to IN63, the bits IN0 to IN7 are provided as they are as output bits OUT0 to OUT7, and the selectors MM8 to MM63 select the bits IN8 to IN63 as output bits OUT8 to OUT63. Namely, the input data is provided as it is as 64-bit output data.
This related art supplies an input bit IN7 to the 56 selectors MM8 to MM63. Namely, the input bit IN7 must drive the gates of the 56 selectors, and long wiring must be laid to transmit the input bit IN7 to the 56 selectors. In this way, the related art applies large load on the input bit IN7, to increase signal delay and decrease operation speed.
To solve this problem, there is an idea of inserting buffers in signal paths for transmitting the input bit IN7. The buffers, however, cause gate delay and increase the size of the circuit 301.
In addition, input bits IN15 and IN31 must drive large load, and therefore, these bits involve the same problem as the bit IN7, although the load on the bits IN15 and IN31 is relatively small compared with that on the bit IN7.
In this way, the related art applies large load on some bits of input data, to increase signal delay and decrease operation speed.